Integrated circuits fabrication places many integrated circuits simultaneously on a single semiconductor wafer. The wafer is then subjected to a process in which individual integrated circuits are seperated from the wafer. At certain stages of fabrication, it is often necessary to polish a surface of the semiconductor wafer.
Semiconductor wafers are often polished to remove high topography surface defects such as crystal lattice damage, scratches, roughness or embedded particles of dirt or dust. This polishing process is often referred to as mechanical planarization (MP). Manufacturing high quality and reliability semiconductor devices usually requires high quality planarization. This process is usually performed during the formation of various devices and integrated circuits on the wafer.
In general, the polishing process involves holding and rotating a thin flat wafer of semiconductor material against a polishing surface under controlled pressure and temperature.
The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates and selectivity between films of the semiconductor surface. This chemical-induced polishing process is often referred to as chemical mechanical planarization (CMP).
FIGS. 1 and 2 show the main components of a conventional polishing apparatus used to polish one face of a semiconductor wafer. A plurality of semiconductor wafers 10 are bonded to the underside surface of a carrier or plate 12 made of glass or other material. First the semiconductor wafers 10 are processed with conventional processing techniques such as lapping, beveling and etching. These wafers are subsequently affixed to the carrier. A material such as wax is typically used so that the wafers can later be removed. A polishing cloth 14 is firmly held on the surface of a turntable 16 which is positioned under the plate 12.
The semiconductor wafers 10 are then brought into contact with the polishing cloth 14 under pressure from the plate 12. At the same time, the turntable 16 rotates to cause the plate 12 to rotate so as to bring the semiconductor wafer 10 into rotating contact with the polishing cloth 14. A polishing slurry including chemical polishing agents is sprayed onto the polishing cloth 14. The polishing slurry typically is a weak alkaline aqueous solution containing colloidal silica as fine abrasive grains which acts to polish the surface of the semiconductor wafer 10.
One problem with this type of polishing process is achieving and maintaining satisfactory flatness. Flatness is important as described above. In addition, photolithographic processes utilized in manufacturing semiconductors need to be in focus during exposure. A high degree of flatness is critical in order to maintain the resolution of the photolithographic lines. These lines can be less than one micron in thickness. The use of stepper lithographic processing heightens the need for a flat wafer surface, particularly on discrete local areas on the surface.
Flatness is quantified, in part, by a total thickness variation measurement (TTV) and site total indicated reading (STIR). TTV is the difference between the maximum and minimum thicknesses of the wafer. STIR is the sum of the maximum positive and negative deviations of the surface in a small area of the wafer from a reference plane, referred to as the focal plane. Total thickness variation in the wafer is a critical indicator of the quality of the polish of the wafer.
Flatness of the polished surfaces of the wafer is not always significantly improved, and may be worsened, by conventional polishing processes. A significant number of wafers will fail to meet flatness and polishing specifications after batch polishing, thus reducing yield in commercial production. Flatness can be worsened by distortions in the wafer. Distortions may be created by the vertical component of the frictional force at the leading edge of a wafer as it encounters an area of particularly high frictional interaction with the polishing pad. A local change in the net vertical force applied to the wafer changes the polishing pressure and the polishing rate of the wafer, thus creating distortions in the polish.
In batch processing, several wafers are rigidly mounted to a single plate, as shown in FIG. 2. Different regions of the polished face may be polished to different degrees because these different regions engage the polishing pad along separate paths. A discontinuity in the pads (e.g., a small lump or an area of glazed slurry) may repeatedly encounter one region of the wafer and not another, causing an imperfection in the polish in one region. Forces and vibrations generated by the interaction of one wafer with the polishing pad are transmitted through the structure of the plate. These forces can undesirably affect the polishing rate and mechanical characteristics of the wafers on the plate. Wafers to be polished by batch processes must be pre-sorted so that all wafers to be mounted at one time on a single plate are of the same thickness to a high degree of accuracy; otherwise, the plate is tilted from the horizontal. This tilting will introduce a non-uniform application of pressure to the wafers on the plate which results in undesirable variations in the polish finish between wafers on the same plate, and throughout the polished surface of each wafer.
The problems of yield associated with batch processing can be alleviated somewhat by single wafer processing, in which each wafer has its own plate. Single wafer processing eliminates the problems of forces transmitted through the pressure plate from one wafer to another. However, single wafer polishing has a very low throughput because only a single wafer per pressure plate is polished at a time. The higher the number of wafers polished simultaneously, the higher the resulting throughput.
Besides these known effects, other factors may also contribute to the unevenness in polishing semiconductor wafers.